1. Field of the Invention
This invention relates to an apparatus for processing an image, such as a character pattern or the like, and more particularly, to an image processing apparatus for generating a pattern of a rotated character or a mirror-image character, or the like.
2. Description of the Related Art
In a conventional character pattern generator of an image processing apparatus, a character code and row assignment are received as address inputs, and the pattern of the corresponding row of the character is obtained as data. FIG. 21 illustrates a conventional character pattern generator for generating a character pattern configured by a dot pattern comprising 8 dots.times.8 dots. In such a character pattern generator 210, the pattern of the corresponding row of a character is output using a character code and row assignments (RA2-RA0). In the case shown in FIG. 21, portion #7 of a storage unit 211 stores the first column of the character pattern, portion #6 stores the second column of the character pattern, and portions #5-#0 store information in the same manner, each corresponding to a column of the character pattern. A character pattern "R" shown in FIG. 22 will now be specifically explained. When reading the character pattern, a character code corresponding to the character pattern "R" is first input to a character-code input unit 214. Subsequently, row assigning codes (RA2, RA1, RA0) are input to a row-assigning-code input unit 212. At that time, if the line assigning codes are (RA2, RA1, RA0)=(0, 0, 0), the left-end pattern, the second pattern from the left, the third pattern from the left, and further in the same manner the right-end pattern of the first row of the character pattern "R" are output from output port Q7 of portion #7, Q6 of portion #6, Q5 of portion #5, and further in the same manner Q0 of portion #0 of the storage unit 211, respectively. Character output pattern 213 becomes (07, 06, 05, 04, 03, 02, 01, 00)=(0, 1, 1, 1, 1, 0, 0, 0), which is the pattern of the first row of the character pattern "R". If the row assigning codes are (RA2, RA1, RA0)=(0, 0, 1), character output pattern 213 outputs (07, 06, 05, 04, 03, 02, 01, 00)=(0, 1, 0, 0, 0, 1, 0, 0), which is the pattern of the second row of the character pattern "R". By these sequentially changing the row assigning codes as (RA2, RA1, RA0)=(0, 0, 0)-(1, 1, 1), a pattern for 8 rows of the character code "R" can be obtained. By arranging the output patterns as shown in FIG. 22, character pattern 221 for the character "R" can be obtained. The relationship between the row assigning codes (RA2, RA1, RA0) and the rows is as shown in FIG. 22.
However, the above-described conventional approach has the disadvantages that, when trying to obtain a rotated/mirror-image character pattern for the same character pattern, complicated additional circuitry is needed, and processing time is increased.
In order to explain the above-described problems, a case wherein character pattern 231 is obtained by rotating the character pattern "R", as shown in FIG. 23, will be considered. The i-th (i=1-8) row of the rotated character corresponds to the i-th column of the original character pattern "R" shown in FIG. 22. In order to obtain the pattern of the third row of the rotated character, the row assigning codes first assign (RA2, RA1, RA0)=(0, 0, 0) for the original character pattern "R" to obtain the output of character output pattern 05. This output corresponds to the right-end pattern of the third row of the rotated character. Subsequently, the row assigning codes assign (RA2, RA1, RA0)=(0, 0, 1) to obtain the output of character output pattern 05. This output corresponds to the second pattern from the right end of the third row of the rotated character. In the same manner, by sequentially changing the row assigning code as (0, 1, 0), (0, 1, 1), (1, 0, 0) (1, 0, 1), (1, 1, 0), (1, 1, 1), latching the outputs of character output pattern 05 at respective accesses, and sequentially arranging the outputs, the pattern of the third row of the rotated character is finally obtained. For other rows, character output patterns are obtained in the same manner as when obtaining the third row of the rotated character.
As described above, in order to obtain the pattern of a certain row of the rotated character, 8 successive accesses are needed, and circuitry for latching one bit necessary at each access and sequentially rearranging latched bits is also needed. Of course, this case represents a character pattern comprising 8 dots.times.8 dots. As the dot-matrix size increase, the number of accesses required for each such rotational or other special output also increases. In order to avoid this problem, it is possible to consider a method wherein the pattern of the rotated character is stored separately, as another character (i.e., "R" is stored twice, once upright and once in the rotated position). However, this approach is not practical because the capacity of the storage unit for storing the character patterns must be greatly increased.
A conventional display control device of an image processing apparatus for storing a character pattern in a video RAM and controlling the display of the pattern is configured as shown in FIG. 29. A displaying operation in such a display control device 290 is performed according to the following procedure. That is, a character pattern generator 293 outputs dot pattern corresponding to a character code according to the assigned character code and row assigning codes. Subsequently, a mode control unit 294 processes the character pattern in accordance with assigned attribute data, and outputs the processed character pattern to a parallel/serial conversion unit 295. Finally, the output is transmitted to a display device 291 via a video signal generation unit 296. As a result, the display device 291 performs display in accordance with the output pattern.
A conventional mode control unit has a circuit configuration as shown in FIG. 30. In such a circuit configuration, the mode control unit can select reverse, secret, blink and a combination of these elements as a display mode.
If it is assured that the above-described modes, reverse, select and blink, are controlled with three kinds of digital signals (0 or 1) independent of one another, in the mode control unit shown in FIG. 30, the signals at "pattern in" are output to "pattern out" when the signals reverse, secret and blink are all 0. Hence, a character pattern stored in the character pattern generator is displayed as it is (this mode will be hereinafter termed the normal mode). When only the reverse signal is 1, the input at "pattern in" is inverted by an exclusive OR circuit (hereinafter termed an exor circuit) without being marked by a logical product circuit (hereinafter termed an AND circuit), and output to "pattern out". Hence, a reversed character pattern is displayed (this mode will be hereinafter termed a reverse mode). When only the secret signal is 1, the input at "pattern in" is masked by the AND circuit, and is output to "pattern out" without being inverted by the exor circuit. Hence, signal "0" is transferred to the display device from the output "pattern out" irrespective of the character pattern (this mode will be hereinafter termed a secret mode). When only the blink signal is 1, the input at "pattern in" is periodically masked by a blink gate signal in the AND circuit, and is not inverted by the exor circuit. Hence, the character pattern and an all "0" pattern are periodically and alternately transferred to the display device (this mode will be hereinafter termed a blink mode). An explanation may be provided in the same manner when any two signals from among the reverse, secret and blink signals are 1, or when all three signals are 1.
If the above-described control is applied to the case of the character pattern "R", any mode may be selected from 8 kinds of mode, as shown in FIG. 31(A), the displays of the character pattern "R" being shown in FIG. 31(B).
An explanation will now be provided how a character pattern is stored and output in the character pattern generator 293. FIG. 32 shows a storage unit which stores a character pattern configured by a dot pattern of 8 dots.times.8 dots for one character. FIG. 33 shows a dot pattern of the character pattern "R" considered in this case. In a conventional approach, a character pattern, for example "R", is stored as it is. That is, portions #7, #6, . . . #0 of a storage unit 321 store only dot patterns of the first column, the second column etc., and the eighth column of respective rows of the character pattern, respectively. Accordingly, when reading the character pattern "R" using row assigning codes 322 comprising 3 bits, if, for example, the fifth row is assigned as (RA2, RA1, RA0)=(1, 0, 0), output 193 of the storage unit becomes (07, 06, 05, 04, 03, 02, 01, 00)=(0, 1, 0, 1, 0, 0, 0, 0), and the dot pattern of the fifth row is output as it is. By thus storing the character pattern as it is, and outputting a dot pattern for every row using row assigning codes, the character pattern is generated.
In the above-described conventional approach however, although it is possible to perform display such as reverse, secret, blink or the like of the corresponding character pattern using one character pattern, in order to display a rotated or mirror-image character pattern, the rotated/mirror-image character pattern must be stored in the character pattern generator in addition to the original character pattern. Accordingly, when displaying a rotated/mirror-image character pattern on the display device, the conventional approach has the disadvantage of greatly increasing the required capacity of the character pattern storage unit.
In a conventional printer device of an image processing apparatus, a character code and its attribute data are converted into the corresponding dot pattern having the form of a matrix according to print data, and the converted dot pattern is transmitted to a print head to perform printing. FIG. 37 is a block diagram showing an example of the configuration of a conventional printer device. A printing operation in such a printer device is performed in the following manner. That is, a character pattern generator 373, serving as a component of a printer device 370, outputs a dot pattern corresponding to an assigned row of a character pattern corresponding to an assigned character code according to the assigned character code and row assigning codes. Subsequently, a mode control unit 374 processes the character pattern in accordance with assigned attribute data, and outputs the processed character pattern to a print head 371 via a print head driver unit 375. As a result, the print head 371 performs printing in accordance with the output pattern.
A conventional mode control unit has, for example, a circuit configuration as shown in FIG. 38. In such a circuit configuration, the mode control unit can select underline, overline, black-and-white reversal of printing (hereinafter termed reversal) and a combination of these elements as a print mode.
If it is assumed that the above-described modes, underline, overline and reversal, are controlled by three kinds of digital signals (0 or 1) independent of one another, in the mode control unit shown in FIG. 38, the signals at "pattern in" are output to "pattern out" when the signals underline, overline and reversal are all 0. Hence, a character pattern stored in the character pattern generator is displayed as it is. When only the reverse signal is 1, the input at "pattern in" is inverted by an exclusive OR circuit, and is output to "pattern out". Hence, a reversed character pattern is printed. When only the underlined signal is 1, the output at "pattern out" of the lowermost row becomes "1" by a logical sum circuit irrespective of the pattern, and the input signals at "pattern in" are output to "pattern out" as they are for other patterns. Hence, a character pattern having an underline is printed (this printing will be hereinafter termed underline). When only the overline signal is 1, a patten wherein the uppermost row is "1" is output to "pattern out" in the same manner as in the underline mode. Hence, a character pattern having an overline is printed (this printing will be hereinafter termed overline). An explanation may be provided in the same manner when any two signals from among the underline, overline and reversal signals are 1, or when all three signals are 1.
If the above-described control is applied to the case of a character pattern "F", any mode may be selected from 8 kinds of modes shown in FIG. 39(A). If printing is performed using such modes, the character pattern "F" appears with the patterns shown in FIG. 39(B).
In the case of normal printing, a print head configured by 8 dots.times.8 dots for one character will now be considered.
A conventional print head is configured so as to vertically arrange print storage, and provide printing mechanisms for respective columns (in this case, the number of printing mechanisms is 8). Referring to FIG. 37, the movement of the print head 371 is controlled by a print head movement control unit 376. The print head movement control unit 376 provides two control digital signals, i.e., a half-step control signal and a double-printing control signal for the print head 371. By combining 0 and 1 of such control signals, print head control can be performed with four kinds of modes as shown in FIG. 40(A). First, when performing normal printing, ever time each column of a character pattern is printed, the print head movement control unit 376 moves the print head in units of a step, and completes printing of one character by printing 8 columns. Subsequently, by printing respective columns of the character pattern twice (double printing), a character pattern having a width twice that for normal printing can be printed (this printing will be hereinafter termed double-size printing). On the contrary, by making the movement of the print head half that for normal printing (half step), a character having a width half that obtained in normal printing can be printed (this printing will be hereinafter termed reduced-size printing). Further, if the print head is moved at half step and double-size printing is performed, a character having the same width as in normal printing and a print density twice that of normal printing can be printed (this printing will be hereinafter termed emphasizing printing). FIG. 40(B) shows an example wherein the above-described control is applied using the character pattern "F".
An explanation will now be provided how a character pattern is stored and output in the character pattern generator 373. FIG. 41(A) shows a storage unit which stores a character pattern configured by a dot pattern of 8 dots.times.8 dots for one character. FIG. 41(B) shows a dot pattern of the character pattern "R" considered in this case. In a conventional approach, a character pattern, for example "R", is stored as it is. That is, portions #7, #6, . . . #0 of a storage unit 411 store only dot patterns of the first row, the second row, etc., and the eighth row of respective columns of the character pattern, respectively. Accordingly, when reading the character pattern "R" using a column assigning code 412 comprising 3 bits, if, for example, the fifth column is assigned as (CA2, CA1, CA0)=(1, 0, 0), output 183 of the storage unit becomes (07, 06, 05, 04, 03, 02, 01, 00)=(1, 0, 0, 1, 0, 1, 0, 0), and the dot pattern of the fifth column is output as it is. By thus storing the character pattern as it is, and outputting a dot pattern for respective columns using column assigning codes, the character pattern is generated.
In the above-described conventional approach, however, although it is possible to perform printing, such as reversal, overline, underline, double-size printing, reduced-size printing, emphasizing printing or the like, of the corresponding character pattern using one character pattern, in order to print a rotated or mirror-image character pattern, the rotated or mirror-image character pattern must be stored in the character pattern generator in addition to the original character pattern. Accordingly, when printing a rotated/mirror-image character pattern by the printer device, the conventional approach has the disadvantage of greately increasing the required capacity of the character pattern storage unit.
In a conventional image processing apparatus for processing a figure pattern or the like, when, for example, writing a character pattern in a memory as image information, or writing the character pattern in a frame memory in order to display it, the character pattern is read from a character pattern storage unit, and written in these memories. A conventional character pattern storage unit 440 of an image processing apparatus has a configuration as shown in FIG. 44. When a character code and a row (raster) are assigned, the portion of the row of the character pattern corresponding to the character code is output. Accordingly, when writing a character pattern subjected to pattern expansion in the memory using such a character pattern storage unit as unit 440, processing as shown in the flowchart of FIG. 46 is performed.
For example, a case wherein a character "R" having a character pattern 450 comprising 8 dots.times.8 dots shown in FIG. 45 is read and written in a memory will be considered. By assigning a character code and row assignment (RA2, RA1, RA0)=(0, 0, 0) in the character pattern storage unit 440, the left-end dot, the second dot from the left, the third dot from the left, and further in the same manner the right-end dot of the first row of the character pattern "R" shown in FIG. 45 are obtained from output ports Q7 of portion #7, Q6 of portion #6, Q5 of portion #5, etc., and Q0 of portion #0 of the storage unit 440, respectively. Character output pattern 141 becomes (07, 06, 05, 04, 04, 03, 02, 01, 00)=(0, 1, 1, 1, 1, 0, 0, 0). Subsequently, by assigning that (RA2, RA1, RA0)=(0, 0, 1), the pattern of the second row of the character pattern "R" (07, 06, 05, 04, 03, 02, 01, 00)=(0, 1, 0, 0, 0, 1, 0, 0) is output. This pattern is written in the next portion of the memory via a register. By thus outputting row assignment (RA2, RA1, RA0)=(0, 0, 0)-(1, 1, 1), and sequentially writing the respective output character patterns 141 in the memory, a pattern for 8 rows of the character code "R" is read and written.
Next a case wherein, for example, a character pattern 470 shown in FIG. 47 obtained by rotating the character pattern "R" shown in FIG. 45 is written in the memory will be considered. In gross, two conventional methods are present: one using software, and other using dedicated hardware.
First, an explanation will be provided of the method using software with reference to the flowchart of FIG. 48(A). First, a character code and row assignment i (i=)0-7) are assigned in the character pattern storage unit 440 (S482). As an example, the character pattern 450 shown in FIG. 45 is read for the amount of one row, and stored in register 1 (S483). By repeating this operation 8 times, the entire character pattern shown in FIG. 45 is stored in registers 0-7 (S482-S485). Subsequently, by shifting register 0 to the left by one bit, the left-end bit of the pattern is written in register c (1-bit register) (S488). As shown in FIG. 48(B), the contents of register c and register 8 are shifted to the right by one bit so as to shift the value of register c to the most significant bit (MSB) (b7) of register 8 (S489). Subsequently, in the same manner, the contents of register 1 are shifted to the left by one bit, and the contents of register 8 are shifted to the right by one bit, whereby the left-end bit of pattern data stored in register 1 is shifted to the MSB of register 8. By repeating such operation to register 7, the left-end bits (MSBs) of respective patterns stored in registers 0-7 are stored, and arranged in register 8, and all the contents of registers 0-7 are shifted to the left by one bit. By writing the contents of register 8 at that time, the first row of the pattern 470 shown in FIG. 47 is written in the memory (S492). Further, in the same manner, by repeating the shift operation of registers 0-7 and register 8 eight times at S 488-S491, the pattern data 470 shown in FIG. 47 are written in the memory at step S492. Thus, pattern data obtained by rotating the character pattern 450 shown in FIG. 45 90.degree. to the right are formed in the memory.
On the other hand, the circuit configuration of suitable known dedicated hardware is as shown in FIG. 49. FIG. 51 shows a flowchart of rotation processing by a write/read control unit. The hardware comprises a pattern rotator 490 for rotating a pattern 90.degree. clockwise. First, a pattern is read by performing row assignment i (i=0-7) from the above-described character pattern storage unit 440 (S512-S513). By making a write control signal WR.sub.i for writing the contents of the read pattern in register block #i of the pattern rotator active, pattern data for one row are written in the register block #i (S514). Each register block 502 has a configuration as shown in FIG. 50, and includes an 8-bit register 501. After writing all the character pattern in register block 491 by making write control signals WR.sub.i (i=0-7) active, data stored in the register block 491 are read by making read control signals RD.sub.0 active. At that time, by making the signal RD.sub.0 active, the contents (8 bits) of bit 7 (the most significant bit) of the register 501 of each register block are output from each register block and transmitted to data bus 493. Hence, the pattern of the first row of the rotated character shown in FIG. 47 is obtained. In the same manner, by reading data by making a read control signal RD.sub.1 active, the pattern of the second row of the rotated character shown in FIG. 47 is obtained. By writing data thus read by sequentially making read control signals RD.sub.0 -RD.sub.7 active in the memory, the rotation operation is completed (S517-S521), and the character pattern shown in FIG. 47 is finally obtained.
The above-described conventional approach, however, has the following disadvantages. That is, in order to obtain the pattern of a rotated or mirror-image character (90.degree. rotation to the right in the above-described example), software or hardware processing is necessary. In software processing, the burden on the bus master (for example, a CPU) is increased, and processing speed becomes much slower than when obtaining the pattern of the original character. In hardware processing, the configuration of hardware (the pattern rotator 490) becomes complicated. Particularly when the size of a character pattern is increased, the overall circuit complexity rises due to the number of bits of a register, selector circuits within respective register blocks, and the circuit configuration of a write/read control unit. Also in this case, processing speed becomes more or less slower than the processing speed of the original character by the amount of writing and reading operation in the pattern rotator. Furthermore, when a plurality of pattern rotators of a number of bits smaller than the size of the character pattern are used in order to reduce the scale of the hardware, (i.e., the pattern rotator, one character pattern must be dealt with dividing it in a plurality of portions, thereby increasing processing time.
Another possible approach wherein a rotated or mirror-image character is registered with another character code and stored in a character storage unit drastically increases the required storage capacity, and so is not practical.
If the rotation of an image is performed only by software, much time is needed for processing. Hence, in most cases, dedicated hardware for image rotation is used. For example, a conventional 8.times.8 (indicating an image comprising 8 lines.times.8 picture elements per line) image rotating device 740 is configured as shown in FIG. 74, and provides an image obtained by rotating an 8.times.88 image 90.degree. clockwise.
An explanation will now be provided of processing for providing an image obtained by rotating 8.times.8 image data 90.degree. clockwise, or to the right, using the above-described image rotating device 740, with reference to a flowchart of rotation processing by a write-read control unit 743 shown in FIG. 76. First, the contents of the i-th row (i=0-7) counted from the head of the image data are written in register block #i of the image rotating device 740 by making the write control signal WR.sub.i active (S102). Picture elements of the image data correspond to D.sub.7 -D.sub.0 from the left in an input buffer unit 744 and a register block 742. As shown in FIG. 75, each register block 741 includes an 8-bit register 751. After writing all the image data for 8 rows in the image rotating device 740 by making the write control signal WR.sub.i (i=0-7) active (S762-S764), data stored in the corresponding register address of the register block 742 are read by making the read control signal RD.sub.0 active. At that time, as can be understood from FIG. 75, if the signal RD.sub.0 is made active, register R.sub.7 for the seventh bit, which is the most significant bit, of each register block 741 becomes active, and the contents (8 bits) of bit 7 (D.sub.7) are output from each register block 741. As a result, the left-end data of each row of the original image, that is, data of the first row of an image obtained by rotating the original image 90.degree. clockwise can be obtained. In the same manner, by reading data by making the read control signal RD.sub.1 active, data of the second row of the image rotated 90.degree. clockwise can be obtained. By outputting data thus read by sequentially making signals RD.sub.0 -RD.sub.7 active via an output data buffer 745 (S766- S768), the output data have been rotated 90.degree. clockwise relative to the input data.
In order to obtain an image rotated 90.degree. counterclockwise using, for example, the image rotating device 740, the first line through the eighth row of the 8.times.8 image are written in register blocks #7-#0, respectively. Although the writing method differs from the writing method in the case of rotating 90.degree. clockwise, the same reading method can be used. The read image is an image rotated 90.degree. counterclockwise from the original image.
The above-described conventional approach, however, has the following disadvantages.
(1) When the capacity of image data is large, circuit complexity increases greatly due to the number of bits of a register, selector circuits within a register block, and the scale of the circuit configuration of a write/read control unit for generating read control signals RD.sub.i and write control signals WR.sub.i. Hence, the practical use of an image rotating device for dealing with image data having large capacity was difficult. Accordingly, when dealing with image data having large capacity, a method has generally been adopted wherein the image data are divided into several portions, each of which is rotated by a small-scale image rotating device, and rotation in units of the divided portion is performed using software. Such a method, however, requires after all a long processing time for software processing.
(2) when reading the same image data performing different rotation or mirror-image processing (in the above-described approach, 90.degree. rotation clockwise and 90.degree. rotation counterclockwise), the same image data must be rewritten number of times proportional to the frequency of processing.
A conventional image processing apparatus 800 for storing image data and controlling, for example, print outputs of the image data is configured as shown in FIG. 80. If it is assumed that the leading address of a storage unit 860 is address 0 (an address as seen from the bus master is obtained by adding an offset address to this address), and input/output of image data is performed in units of 8 picture elements, and the image data are stored in the storage unit 860 such that, as shown in FIG. 81, a predetermined number of picture elements laterally arranged in the upper left of the image data (8 picture elements in the case of FIG. 81) are stored in address 0. The next right 8 picture elements are stored in address 1, and the remaining picture elements are sequentially stored in the same manner to the 8 picture elements in the final column. The left-end picture elements on the next row are stored in the rear (not always immediately next) address portion of the final column, and picture elements on that row are sequentially stored in the storage unit in the same manner.
Accordingly, as shown in FIG. 81, the address of two-dimensional data, such as image data, in units of data (8 picture elements in the present case) in the storage unit on the y-th row counted from 0 and the x-th column counted from 0 is expressed by (pitch.times.y+x), where the pitch indicates the value of the final address on each row in the storage unit arranged in the form of a matrix, and pitch .gtoreq. the length of a column of image data (hereinafter termed the col.end). Usually, from the viewpoint of easiness of dealing with addresses in software, and simplification of peripheral circuitry of hardware, a numerical value (2.sup.n) having a power of 2 is used as the value of the pitch. By adopting such a value, for example, an address in the storage unit during a printing operation generated in a printer control unit 830 of the image processing apparatus 800 shown in FIG. 80 may be obtained by merely connecting respective outputs from a counter for counting in the row direction and a counter for counting in the column direction, and so an arithmetic circuit is not needed.
Next, an explanation will be provided of the case of a printer, such as a laser-beam printer, which transmits and prints data for every line of an image. It is assumed that the printer has the configuration shown in FIG. 80. FIG. 83 illustrates waveforms of various kinds of signals indicating timings during printing. When it is desired to write image data in the storage unit 860 or print edited image data, a bus master 810 issues a print request command to a bus control unit 820. The bus control unit 820 generates a print request signal after receiving the print request command, and transmits the print request signal to the printer control unit 830, which transmits the request to a printer (not shown) via a printer I/F unit 840. After preparing for printing, the printer issues a synchronizing signal in units of a page. FIG. 82 is a block diagram of the inside of the printer control unit 830. The printer control unit 830 clears values in two counters, i.e., a column-direction counter 821 and a line-direction counter 822, to zero by the synchronizing signal in units of a page shown in FIG. 83, generates a print-enable signal, controls so as to switch an address selector unit 880 to an address during printing, and transmits a print data request signal to the bus control unit 820. Outputs from the two counters 821 and 822 are connected, and the connected signal is provided as an address for the storage unit 860 via an address selector unit 880. Accordingly, address 0 is assigned as the address of the storage unit 860 when issuing the synchronizing signal in units of a page, and at the same time the print data request signal is transmitted to the bus control unit 820, whereby a control signal is transmitted from the bus control unit 820 to the storage unit 860, and data stored in address 0 are transmitted to the printer via an output data buffer 870 and the printer I/F 840. When the next timing clock signal has been issued, only the column-direction counter 821 is incremented, and at the same time a print data request signal is issued, whereby data stored in address 1 of the storage unit 860 are transferred to the printer as print data. The same operation is repeated until the value of the column-direction counter becomes col.end. At that time, the printer control unit 830 recognized that it has transmitted image data for one line to the printer. Hence, the printer control unit 830 changes the state of the column-direction counter 821 from count enable to disable, stops the generation of the print data request signal, and assumes a state of awaiting a synchronizing signal in units of a line. On the other hand, after preparing for a printing operation for the next line, the printer issues a synchronizing signal in units of a line. At that time, the printer control unit 830 clears the column-direction counter 821 to zero, increments the line-direction counter 822, and generates again a print data request signal. Subsequently, the contents of address (x+pitch) of the storage unit 860 are transmitted to the printer. Thus, print data for the second line are sequentially transmitted by intermittently-issued timing clock signals. In such a way, print data for one line are transmitted at every synchronizing signal in units of a line. When the last data on the final line have been transmitted, the output of the column-direction counter 821 becomes col.end, and the output of the line-direction counter 822 becomes line.end (the value of the final line of the image data). When detecting these values col.end and line.end, the printer control unit 830 generates a print end signal, thereby setting the print enable signal in a disable state. At that time, the bus control unit 820 is made to receive an access from the bus master 810, and the address selector 880 is switched so as be able to receive an access from the bus master 810.
The above-described conventional approach, however, has the following disadvantages.
That is, usually, cut sheets which can be used in a printer comprise paper not square in size, such as A4, A5, B4 or the like. The image processing apparatus stores image data in accordance with the size of paper, and performs editing of the data. Although some image processing apparatuses can deal with two directions, i.e., vertically-long and horizontally-long directions, of the same paper when performing print output of the data, most apparatuses support print output of only one direction, for example vertically-long direction, of paper for reasons relating to production cost and the like. In such a case, in order to perform print output of a horizontal-long image edited by the image processing apparatus, an image rotated by 90.degree. must be transmitted to the printer. However, in the above-described conventional approach, software processing is needed in order to obtain data of the rotated image, and the load on the bus master is increased for that processing. As a result, during print output, other processing cannot be performed, or the speed of other processing is greatly reduced.
By the same reason, also when performing print output of a mirror image (reversal) of stored image data, the load on the bus master is increased. As a result, during print output, other processing cannot be performed, or the speed of other processing is greatly reduced.
A conventional image processing apparatus for storing image data and controlling the display of the image is configured as shown in FIG. 85. For the purpose of explanation, it is assumed that the unit of input/output of image data of the image processing apparatus is 8 bits, and image data comprise one bit for one picture element. If the leading storage address of a storage unit 851 is assumed to be address 0 (an address as seen from the bus master is obtained by adding an offset address to this address), image data having a two-dimensional matrix structure are sequentially stored starting from the upper left end from address 0 to address col.end of a storage unit 851 in the direction of columns for respective 8 picture elements on the first row, as shown in FIG. 86. Subsequently, image data for the second row are stored from address pitch to address (pitch+col.end). Further, in the same manner, the image data are stored in the storage unit 851 until the final row (row.end). In general, pitch.gtoreq.col.end. Usually, from the viewpoint of easiness of dealing with addresses in software, and simplification of peripheral circuitry of hardware, a numerical value (2.sup.n) having a power of 2 is used as the value of the pitch.
Accordingly, the address of the storage unit 851 wherein the x-th data counted from 0 in units of 8 picture elements on the y-th row counted from 0 are stored is expressed by (pitch.times.y+x). If the storage address is thus defined, an address in the storage unit 851 generated in a display device control unit 852 may be obtained by merely connecting respective outputs form a counter for counting in the horizontal direction and a counter for counting in the vertical direction, and so an arithmetic circuit is not needed.
Next, an explanation will be provided of a procedure of transmitting image data to a display device comprising, for example, a raster-scanning-type CRT display (hereinafter termed a CRT). In image data display using a raster-scanning method, in general, the CRT is scanned from the left to the right to sequentially display every picture element. When scanning reaches the right end, scanning returns to the left end without performing display. By repeating this operation, picture elements on every line are displayed from above to below. In such scanning, the timing of scanning in the horizontal direction is based on a horizontal synchronizing signal (hereinafter termed an HSYNC signal). If scanning reaches the lowermost portion of the CRT while continuing scanning in the horizontal direction, scanning is returned to the uppermost portion of the CRT without performing display. The same operation is repeated thereafter. The timing of scanning in the vertical direction is based on a vertical synchronizing signal (hereinafter termed a VSYNC signal). FIG. 87 schematically illustrates the way of scanning. In FIG. 87, solid lines represent scanning while performing display, and broken lines represent scanning in a state of not performing display. FIGS. 88 and 89 are block diagrams of the display device control unit 852 and a display device I/F unit 853, respectively. The display device control unit 852 clears a vertical-direction counter 882 by a VSYNC signal, and clears a horizontal-direction counter 881 by an HSYNC signal which follows. A LOAD signal from the display device I/F unit 853 is transmitted to the display device control unit 852, which generates a display enable signal according to the LOAD signal to switch an address selector unit 854 to an address during display, and also generates a display data request signal to request the storage unit 851 to transfer image data. The display device I/F unit 853 generates a VSYNC signal and an HSYNC signal, serving as synchronizing signals for the display device, and a blank signal indicating a non-display period, latches image display data (for 8 picture elements in this case) transmitted from the storage unit in a parallel/serial converter 891 by the LOAD signal, and transmits serialized data to the display device. A blank signal indicating a non-display period relative to horizontal-direction scanning will be termed an HBLANK signal, and a blank signal indicating a non-display period relative to vertical-direction scanning will be termed a VBLANK signal. FIG. 90 is a timing chart of control signals for scanning the CRT in order to display image data. FIG. 91 is a timing chart which shows control timings of one-line scanning when starting display in detail. Outputs of the above-described two counters (the horizontal-direction counter and the vertical-direction counter) are connected to provide an storage address to the storage unit 851 via an address selector unit 854. First, when starting display, the address of the storage unit 851 is set to address 0. When a display data request signal has been transmitted to a bus control unit 855, a control signal is transmitted from the bus control unit 855 to the storage unit 851, and data of 8 picture elements at the upper left end of image data stored in address 0 are transmitted to the display device I/F unit 853 as display data. At the timing of the next display data request signal turned on, only the horizontal-direction counter 881 is incremented, and image data stored in address 1 of the storage unit 851 are transmitted to the display device as display data. Subsequently, in the same manner, the transmission of image data is repeated until an HBLANK signal is turned on. When an HBLANK signal has been turned on, the display of image data for one line has been completed. By the generation of the next HSYNC signal, in the display device control unit 852, the horizontal-direction counter 881 is cleared, the vertical-direction counter 882 is incremented, and transfer of image data for the next line is started. Address (pitch.times.1) is transmitted to the storage unit 851 as an address, an image data for the second line are output from the storage unit 851 as display data. Thus, image data for one line are transmitted to the display device at every HSYNC signal. When the last data of the final line have been transmitted, a VBLANK signal is turned on. At the next VSYNC signal, scanning is resumed from the upper-left end of the CRT. Subsequently, this operation is repeated.
In the above-described conventional approach, however, a reading operation for image data for one line is synchronized with the timing of an HSYNC signal. Hence, when a vertically-long CRT is adopted, if it is attempted to continue scanning with the same frequency of the VSYNC signal as in a horizontally-long CRT, the frequency of the HSYNC signal must be increased in order to suppress flicker on the CRT picture surface. However, if the frequency of the HSYNC signal is increased, it is necessary to increase reading speed of image data from the storage unit, necessitating adoption of a high-speed memory in the storage unit. Furthermore, in order to increase the frequency of the HSYNC signal, current flowing through the deflection yoke (a coil for controlling the magnetic field in order to deflect electrons emitted from the electric gun) within the CRT must by increased, causing problems of heat generation and requiring higher-grade components. As a result, the conventional approach has the disadvantage of increasing the cost of a vertically-long CRT.
A conventional image processing apparatus for storing and editing image data transmitted from an image input device is configured as shown in FIG. 93. Image data are stored in a storage unit 931 in the following manner: If the leading address of the storage unit 931 is assumed to be address 0 (an address as seen from a bus master 932 is obtained by adding an offset address to this address), a predetermined number of picture elements laterally arranged in the upper left of the image data (8 picture elements in the case of FIG. 93) are stored in address 0. The next right 8 picture elements are stored in address 1, and the remaining picture elements are sequentially stored in the same manner until 8 picture elements in the portion of col.end. The left-end picture elements on the next row are stored in the rear (not always immediately next) address portion of the col.end, and picture elements on that row are sequentially stored in the storage unit 931 in the same manner.
Accordingly, as shown in FIG. 94, the address of the storage units wherein the x-th data counted from 0 in units of 8 picture elements on the y-th row counted from 0 is expressed by (pitch.times.y+x), where pitch.gtoreq.col.end. Usually, from the viewpoint of easiness of dealing with addresses in software, and simplification of peripheral circuitry of hardware, a numerical value (2.sup.n) having a power of 2 is used as the value of the pitch. In this case, an address in the storage unit 931 when inputting image data generated by a scanner controls unit may be obtained by merely connecting respective outputs from a counter for counting in the row direction and a counter for counting in the column direction, and so an arithmetic circuit is not needed.
An explanation will now be provided of a scanner which transfers every picture element of image data in the row direction (main spanning), and transfers every line from above to below (sub-scanning). FIG. 97 illustrates timing when inputting image data. As shown in FIG. 93, if it is desired to input image data from the scanner, a bus master 932 issues a scanner input request. A bus control unit 933 generates a scan req. signal according to the scanner input request, and transmits the scan req. signal to a scanner control unit 934. The scanner control unit 934 transmits the request to the scanner via a scanner I/F unit 935. After preparing for the transfer of image data, the scanner outputs data serialized in units of a picture element and a timing clock signal for receiving the data together with a data valid signal. FIGS. 95 and 96 are block diagrams of the scanner I/F unit 935 and the scanner control unit 934.
FIG. 97 is a timing chart. An explanation will now be provided of an operation according to this timing chart. Before the scanner transmits image data, a valid signal (HE signal) in units of a page is made low. Hence, flip-flops 957, 963 and 964 are cleared, whereby a 3-bit counted 952, a column-direction counter 961 and a row-direction counter 962 are cleared, respectively. At that time, an address (RCNTn.CCNtn) transmitted from the scanner control unit 934 to an address selector unit 936 becomes 0, which address is an address storing data at the upper-left end of the storage unit 931. When the scanner has prepared for the transfer of image data, the data valid signal in units of a page becomes high, and at the same time the scan enable signal becomes high, whereby the address selector unit 936 switches the signal to be added to the address of the storage unit 931 from the address of the bus master 932 to outputs from the column-direction counter 961 and the row-direction counter 962 of the scanner control unit 934. The bus master 932 can know the above-described processing via the bus control unit 933. Subsequently, since the valid signal in units of a line becomes high, the output of the flip-flop 964 becomes high, whereby the cleared state of the row-direction counter 962 is released (its output RCNTn remains 0). Subsequently, serialized image data (VD signals) are transmitted from the scanner together with clock signals. By the first clock signal, the first VD signal is latched by a serial/parallel conversion unit (S/P unit) 951, the output of the flip-flop 957 becomes high, and the cleared state of the 3-bit counter 952 is released. By the next clock signal, the next VD signal is latched by the S/P unit 951, and the 3-bit counter 952 starts counting to have the value 1. At the 8-th clock signal, the conversion of the serialized image data into 8-picture-element parallel data has been completed, and the carry output of the 3-bit counter 951 becomes high, making the scan data valid signal high. By the scan data valid signal, the output of the flip-flop 963 becomes high, and the cleared state of the column-direction counter 961 is released (its output CCNTn remains 0). The scan data valid signal is transmitted to the bus control unit 933 to notify that data to be written in the storage unit 931 are prepared. The bus control unit 933 write the data from the scanner in the storage unit 931 before the completion of the conversion of the next 8-picture-element data into parallel data. Since the address of the storage unit 931 at that time is address 0 because address RCNTn.CCNTn is 0, the first 8-picture-element data are written in address 0. By the succeeding 8 clock signals, the next 8-picture-element data are prepared in the S/P unit 951 in the same manner, and a scan data valid signal is output according to the carry output of the 3-bit counter 952. Since the column-direction counter 961 is incremented by this scan data valid signal, the 8-picture-element data at that time are written in address 1 of the storage unit 931. By repeating this operation, image data for the first row are written in continuous addresses starting from address 0. After transferring image data for one row, the scanner makes the valid signal in units of a row low. Hence, the flip-flops 957, 963 are cleared, and the 3-bit counter 952 and the column-direction counter 961 are cleared again. After the completion of the preparation of the transfer of image data for the next row, the scanner makes again the valid signal in units of a row high. At that time, the row-direction counter 962 is incremented. As a result, the address of the storage unit 931 becomes address (pitch.times.1). Subsequently, the scanner transfers image data for the next row with repeating the same operation as in the case of the first row. Hence, the image data for the second row are written in continuous addresses starting from address (pitch.times.1) of the storage unit 931. The same operation is performed for image data for rows after the third row. After the completion of the transfer of all image data, the scanner makes the valid signal in units of a page low, whereby the scan enable signal becomes low, and the address selector unit 936 switches so as to add the address of the bus master 932 as the address of the storage unit 931. Accordingly, the bus master 932 can read image data from the scanner stored in the storage unit 931, and can edit the image data by changing the contents of the storage unit 931.
Usually, copy paper which can be used in a scanner comprises paper not square in size, such as A4, A5, B4 or the like. An image processing apparatus reads, stores and edits images in accordance with the size of paper. Some image processing apparatuses can deal with two directions, i.e., vertically-long and horizontally-long directions, of the same paper. No problem will arise if the scanner supports the two directions. However, if the scanner supports only one direction, for example the vertically-long direction, of paper for reasons relating to production cost and the like, when dealing with a horizontally-long image, image data transferred from the scanner must be rotated by 90.degree. in the image processing apparatus. However, in the above-described conventional approach, software processing is needed in order to obtain data of the rotated image, increasing the load of the bus master 932 for that processing. As a result, the conventional approach has the disadvantage that other processing cannot be performed during an image reading operation.
By the same reason, also when storing a mirror image (reversal) of image data input from the scanner, the conventional approach has the disadvantage that the load of the bus master 932 is increased.